2. Identify the circuit below, and its limitation.
3. Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compared to path A. How do we solve this problem if the propagation delay in path B can not be reduced ?
4. What is the function of a D flip-flop, whose inverted output is connected to its input ?
5. Design a circuit to divide input frequency by 2.
6. What are the different types of adder implementations ?
7. What are the different types of adder implementations ?
8. Give the truth table for a Half Adder. Give a gate level implementation of it.
9. What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a buffer ?
10. What is the output of the circuit below, assuming that value of 'X' is not known ?
11. Consider a circular disk as shown in the figure below with two sensors mounted X, Y and a blue shade painted on the disk for an angle of 45 degree. Design a circuit with minimum number of gates to detect the direction of rotation
12. Design an OR gate from 2:1 MUX.(This is one of the most commonly asked interview questions)
13. Design an XOR gate from 2:1 MUX and a NOT gate
14. What is the difference between a LATCH and a FLIP-FLOP ?
16. What is metastable state ? How does it occur ?
17. What is metastability ?
18. Design a 3:8 decoder
19 Design a FSM to detect sequence "101" in input sequence.
20 Convert NAND gate into Inverter, in two different ways.
21 Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.
22 Design a divide by two counter using D-Latch.
23 Design D Latch from SR flip-flop.
24 Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
25 What is Race Condition ?
26 Design a 4 bit Gray Counter.
27 Design 4-bit Synchronous counter, Asynchronous counter.
28 Design a 16 byte Asynchronous FIFO.
29 What is the difference between an EEPROM and a FLASH ?
30 What is the difference between a NAND-based Flash and a NOR-based Flash ?
31 You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50% duty cycle.
32 Design a Read on Reset System ?
33 Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.
34 Design a State machine for Traffic Control at a Four point Junction.
35 What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?
36 How can you generate random sequences in digital circuits?
All these are common digital interview questions which you might come across in interviews at campus level.